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datasheet real-time clock with i 2 c serial interface IDT1337G idt? real-time clock with i 2 c serial interface 1 IDT1337G rev m 073013 general description the IDT1337G device is a low power serial real-time clock (rtc) device with two programmable time-of-day alarms and a programmable square-wave output. address and data are transferred serially through an i 2 c bus. the device provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with am/pm indicator. applications ? telecommunication (routers, switches, servers) ? handhelds (gps, pos terminals, mp3 players) ? set-top box, digital recording, ? office (fax/printers, copiers) ? medical (glucometer, medicine dispensers) ? other (thermostats, vending machines, modems, utility meters, digital photo frame devices) features ? real-time clock (rtc) counts seconds, minutes, hours, day, date, month, and year with leap-year compensation valid up to 2100 ? packaged in 8-pin msop, 8-pin soic, 16-pin vfqfpn (without integrated crystal), or 16-pin soic (surface-mount package with an integrated crystal) ? i 2 c serial interface (normal and fast modes) ? two time-of-day alarms ? oscillator stop flag ? programmable square-wave output defaults to 32 khz on power-up ? operating voltage of 1.8 to 5.5 v ? industrial temperature range (-40 to +85c) block diagram scl sda crystal inside package for 16-pin soic only x1 x2 1 hz/4.096 khz/ 8.192 khz/32.768 khz sqw/intb i 2 c interface 32.768 khz oscillator and divider control logic mux/ buffer clock, calendar counter 1 byte control 7 bytes buffer alarm registers inta vcc gnd
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 2 IDT1337G rev m 073013 pin assignment (8-pin msop/soic) pin assignment (16-pin soic) pin assignment (16-pin vfqfpn) x1 inta scl sqw/intb gnd vcc 1 2 3 4 8 7 6 5 sda x2 IDT1337G 16 1 15 2 14 3 13 4 5 6 7 8 9 10 12 11 scl vcc nc nc nc nc nc nc nc nc nc nc sda gnd inta sqw/intb IDT1337G 1 5 9 13 nc inta gnd nc sda nc nc scl nc x1 x2 nc nc vcc sqw/intb nc
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 3 IDT1337G rev m 073013 pin descriptions pin number pin name pin description/function msop soic qfn 1 ? 14 x1 connections for standard 32.768 kh z quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (cl) of 7 pf. an external 32.768 khz oscillator can also drive the IDT1337G. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is left floating. 2? 15 x2 314 2 inta interrupt output. when enabled, inta is asserted low when the time/day/date matches the values set in the alarm registers. this pin is an open-drain output and requires an external pull-up resistor (10 k ? typical). 4 15 3 gnd connect to ground. dc power is provided to the device on these pins. 5 16 6 sda serial data input/output. sda is the input/output pin for the i 2 c serial interface. the sda pin is an open-drain output and requires an external pull-up resistor (2 k ? typical). 6 1 7 scl serial clock input. scl is used to synchronize data movement on the serial interface. the scl pin is an open-drain output and requires an external pull-up resistor (2 k ? typical). 7 2 10 sqw/intb square-wave/interrupt output. programmable square-wave or interrupt output signal. the sqw/int pin is an open-drain output and requires an external pull-up resistor (10 k ? typical). this pin can also function as an additional interrupt pin under certain conditions (see page 6 for details). 8 3 11 vcc primary power supply. dc power is applied to this pin. ? 4 - 13 1,4,5,8,9, 12,13,16 nc no connect. these pins are unused and must be connected to ground.
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 4 IDT1337G rev m 073013 typical operating circuit detailed description communications to and from the IDT1337G occur serially over an i 2 c bus. the IDT1337G operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification code, followed by data. subsequent registers can be accessed sequentially until a stop condition is executed. the device is fully accessible through the i 2 c interface whenever vcc is between 5.5 v and 1.8 v. i 2 c operation is not guaranteed when vcc is below 1.8 v. the IDT1337G maintains the time and date when vcc is as low as 1.3 v. the following sections discuss in detail the oscillator block, clock/calendar register block and serial i 2 c block. oscillator block selection of the right crystal, correct load capacitance and careful pcb layout are important for a stable crystal oscillator. due to the optimization for the lowest possible current in the design for these oscillators, losse s caused by parasitic currents can have a significant impact on the overall oscillator performance. extra care needs to be taken to maintain a certain quality and cleanliness of the pcb. crystal selection the key parameters when selecting a 32 khz crystal to work with IDT1337G rtc are: ? recommended load capacitance ? crystal effective series resistance (esr) ? frequency tolerance effective load capacitance please see diagram below for effective load capacitance calculation. the effective load capacitance (cl) should match the recommended load capacitance of the crystal in order for the crystal to oscilla te at its specified parallel resonant frequency with 0ppm frequency error. in the above figure, x1 and x2 are the crystal pins of our device. cin1 and cin2 are the internal capacitors which include the x1 and x2 pin capacitance. cex1 and cex2 are the external capacitors that are needed to tune the crystal frequency. ct1 and ct2 are the pcb trace capacitances between the crystal and the device pins. cs is the shunt capacitance of the crystal (as specified in the crystal manufacturer's datasheet or measured using a network analyzer). cpu x1 x2 v cc sqw/intb inta gnd sda scl crystal IDT1337G v cc 2k 2k v cc v cc 10k 10k
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 5 IDT1337G rev m 073013 note : idt1337csri integrates a standard 32.768 khz crystal in the package and contributes an additional frequency error of 10ppm at nominal v cc (+3.3 v) and t a = +25c. esr (effective series resistance) choose the crystal with lower esr. a low esr helps the crystal to start up and stabilize to the correct output frequency faster compared to high esr crystals. frequency tolerance the frequency tolerance for 32 khz crystals should be specified at nominal temperature (+25c) on the crystal manufacturer datasheet. the crystals used with IDT1337G typically have a frequency tolerance of +/-20ppm at +25c. specifications for a typical 32 khz crystal used with our device are shown in the table below. pcb design consideration ? signal traces between idt device pins and the crystal must be kept as short as possible. this minimizes parasitic capacitance and sensitivity to crosstalk and emi. note that the trace capacitances play a role in the effective crystal load capacitance calculation. ? data lines and frequently switching signal lines should be routed as far away from the crystal connections as possible. crosstalk from these signals may disturb the oscillator signal. ? reduce the parasitic capacitance between x1 and x2 signals by routing them as far apart as possible. ? the oscillation loop current flows between the crystal and the load capacitors. this signal path (crystal to cl1 to cl2 to crystal) should be kept as short as possible and ideally be symmetric. the ground connections for both capacitors should be as cl ose together as possible. never route the ground connection between the capacitors all around the crystal, because this long ground trace is sensitive to crosstalk and emi. ? to reduce the radiation / co upling from oscillator circuit, an isolated ground island on the gnd layer could be made. this ground island can be connected at one point to the gnd layer. this helps to keep noise generated by the oscillator circuit locally on this separated island. the ground connections for the load capacitors and the oscillator should be connected to this island. pcb layout pcb assembly, soldering and cleaning board-assembly production process and assembly quality can affect the performance of the 32 khz oscillator. depending on the flux material used, the soldering process can leave critical residues on the pcb surface. high humidity and fast temperature cycles that cause humidity condensation on the printed circuit board can create process residuals. these process residuals cause the insulation of the sensitive o scillator signal lines towards each other and neighboring signals on the pcb to decrease. high humidity can lead to moisture condensation on the surface of the pcb and, together with process residuals, reduce the surface resistivity of the board. flux residuals on the board can cause leakage current paths, especially in humid environments. thorough pcb cleaning is therefore highly recommended in order to achieve maximum performance by removing flux residuals from the board after assembly. in general, reduction of losses in the oscillator circuit leads to better safe ty margin and reliability. parameter symbol min typ max units nominal freq. f o 32.768 khz series resistance esr 80 k ? load capacitance c l 7pf 1337g
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 6 IDT1337G rev m 073013 address map table 2 (timekeeper registers) shows the address map for the IDT1337G registers. during a multibyte access, when the address pointer reaches the end of the register space (0fh), it wraps around to location 00h. on an i 2 c start, stop, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re-read the registers in case of an update of the main registers during a read. table 1. timekeeper registers note : unless otherwise specified, t he state of the registers are not defined when power is first applied or when vcc falls below th e v cct min address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 10 seconds seconds seconds 00 - 59 01h 0 10 minutes minutes minutes 00 - 59 02h 0 12/24 am /pm 10 hour hour hours 1 - 12 + am/pm 00 - 23 10 hour 03h00000 day day 1 - 7 04h 0 0 10 date date date 01 - 31 05h century 0 0 10 month month month/century 01 - 12 + century 06h 10 year year year 00 - 99 07h a1m1 10 seconds seconds alarm 1 seconds 00 - 59 08h a1m2 10 minutes minutes alarm 1 minutes 00 - 59 09h a1m3 12/24 am /pm 10 hour hour alarm 1 hours 1 - 12 + am/pm 00 - 23 10 hour 0ah a1m4 dy/dt 10 date day, alarm 1 day 1 - 7 date alarm 1 date 1 - 31 0bh a2m2 10 minutes minutes alarm 2 minutes 00 - 59 0ch a2m3 12/24 am /pm 10 hour hour alarm 2 hours 1 - 12 + am/pm 00 - 23 10 hour 0dh a2m4 dy/dt 10 date day, alarm 2 day 1 - 7 date alarm 2 date 1 - 31 0eh eosc 0 0 rs2 rs1 intcn a2ie a1ie control 0fhosf00000a2fa1fstatus
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 7 IDT1337G rev m 073013 clock and calendar the time and calendar information is obtained by reading the appropriate register bytes. the rtc registers are illustrated in table 1. the ti me and calendar are set or initialized by writing the appro priate register bytes. the contents of the time and calendar registers are in the binary-coded decimal (bcd) format. the day-of-week register increments at midnight. values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero. the countdown chain is reset whenever the seconds register is written. write transfers occur on the acknowledge pulse from the device. to avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. the 1hz square-wave output, if enable, transitions high 500ms after the seconds data transfer, prov ided the oscillator is already running. the IDT1337G can be run in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am /pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20?23 hours). all hours values, including the alarms, must be reinitia lized whenever the 12/24 -hour mode bit is changed. the century bit (bit 7 of the month register) is toggled when the years register overflows from 99?00. alarms the IDT1337G contains two time of day/date alarms. alarm 1 can be set by writing to registers 07h to 0ah. alarm 2 can be set by writing to registers 0bh to 0dh. the alarms can be programmed (by the intcn bits of the control register) to operate in two different modes?each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. bit 7 of each of the time-of-day/date alarm registers are mask bits (table 1). when all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h?06h match the values stored in the time-of-day/date alarm registers. the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 2 (alarm mask bits table) shows the possible settings. configurations not lis ted in the table result in illogical operation the dy/dt bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. if dy/dt is written to a logic 0, the alarm is the result of a match with date of the month. if dy/dt is written to a logic 1, the alarm is the result of a match with day of the week. when the rtc register values match alarm register settings, the corresponding alarm flag (?a1f? or ?a2f?) bit is set to logic 1. if the corresponding alarm interrupt enable (?a1ie? or ?a2ie?) is also set to logic 1, the alarm condition activates one of the interrupt output (inta or sqw/intb ) signals. the match is tested on the once-per-second update of the time and date registers.
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 8 IDT1337G rev m 073013 table 2. alarm mask bits special-purpose registers the IDT1337G has two additional registers (control and status) that control the rtc, alarms, and square-wave output. control register (0eh) bit 7: enable oscillator (eosc ). this active-low bit when set to logic 0 star ts the oscillator. when this bit is set to a logic 1, the oscillator is stopped . this bit is enabled (logic 0) when power is first applied. bits 4 and 3: rate select (rs2 and rs1). these bits control the frequency of the square-wave output when the square wave has been enabled. table 3 shows the square-wave frequencies that can be selected with the rs bits. these bits are both set to logic 1 (32 khz) when power is first applied. table 3. sqw/int output dy/dt alarm 1 register mask bits (bit 7) alarm rate a1m4 a1m3 a1m2 a1m1 x1111alarm once per second. x1110alarm when seconds match. x1100alarm when minutes and seconds match. x1000alarm when hours, minutes, and seconds match. 00000alarm when date, hours, minutes, and seconds match. 10000alarm when day, hours, minutes, and seconds match. dy/dt alarm 2 register mask bits (bit 7) alarm rate a2m4 a2m3 a2m2 x 1 1 1 alarm once per minute (00 seconds of every minute). x 1 1 0 alarm when minutes match. x 1 0 0 alarm when hours and minutes match. 0 0 0 0 alarm when date, hours, and minutes match. 1 0 0 0 alarm when day, hours, and minutes match. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc 0 0 rs2 rs1 intcn a2ie a1ie intcn rs2 rs1 sqw/intb output a2ie 000 1 hz x 0 0 1 4.096 khz x 0 1 0 8.192 khz x 0 1 1 32.768 khz x 1xx a2f 1
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 9 IDT1337G rev m 073013 bit 2: interrupt control (intcn). this bit controls the relationship between the two alarms and the interrupt output pins. when the intcn bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers activate the inta pin (provided that the alarm is enabled) and a match between the timekeeping registers and the alarm 2 registers activates the sqw/intb pin (provided that the alarm is enabled). when the intcn bit is set to logic 0, a square wave is output on the sqw/intb pin and alarm 2 registers activates the inta pin (provided that the alarm is enabled). alarm 1 registers have no effect on the inta pin.this bit is set to logic 0 when power is first applied. bit 1: alarm 2 interrupt enable (a2ie). when set to a logic 1, this bit permits the alarm 2 flag (a2f) bit in the status register to assert inta (when intcn = 0) or to assert sqw/intb (when intcn = 1). when the a2ie bit is set to logic 0, the a2f bit does not initiate an interrupt sign al. the a2ie bit is disabled (logic 0) when power is first applied. bit 0: alarm 1 interrupt enable (a1ie). when set to logic 1, this bit permits the alarm 1 flag (a1f) bit in the status register to assert inta (when intcn = 1). it does not assert any interrupt pins when intcn=0. when the a1ie bit is set to logic 0, the a1f bit does not initiate the inta signal. the a1ie bit is disabled (logic 0) when power is first applied. status register (0fh) bit 7: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. this bit is set to logic 1 anytime the oscillator stops. the follo wing are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltage pres ent on vcc is insufficient to support oscillation. 3) the eosc bit is turned off. 4) external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. this bit can only be written to a logic 0. bit 1: alarm 2 flag (a2f). a logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. this flag can be used to generate an interrupt on either inta or sqw/intb depending on the status of the intcn bit in the control register. if the intcn bit is set to logic 0 and a2f is at logic 1 (and a2ie bit is also logic 1), the inta pin goes low. if the intcn bit is set to logic 1 and a2f is logic 1 (and a2ie bit is also logic 1), the sqw/intb pin goes low. a2f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. bit 0: alarm 1 flag (a1f). a logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. if the a1ie bit is also a logic 1, the inta pin goes low. a1f is cleared when wr itten to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osf00000a2fa1f
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 10 IDT1337G rev m 073013 i 2 c serial data bus the IDT1337G supports the i 2 c bus protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions must control the bus. the IDT1337G operates as a slave on the i 2 c bus. within the bus specifications, a standard mode (100 khz maximum clock rate) and a fast mode (400 khz maximum clock rate) are defined. the IDT1337G works in both modes. connections to the bus are made via the open-drain i/o lines sda and scl. the following bus protocol has been defined (see the ?data transfer on i 2 c serial bus? figure): ? data transfer may be initiate d only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the cl ock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiate d with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions are not limited, and are determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition.
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 11 IDT1337G rev m 073013 data transfer on i 2 c serial bus depending upon the state of the r/w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data is transferred with the most significant bit (msb) first. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. data is transferred with the most significant bit (msb) first. the IDT1337G can operate in the following two modes: 1) slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit (see the ?data write?slave receiver mode? figure). the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7-bit IDT1337G address, which is 1101000, followed by the direction bit (r/w ), which is 0 for a write. after receiving and decoding the slave address byte the device outputs an acknowledge on the sda line. after the IDT1337G acknowledges the slave address + write bit, the master transmits a register address to the IDT1337G. this sets the register pointer on the IDT1337G. the master may then transmit zero or more bytes of data, with the IDT1337G acknowledging each byte received. the address pointer increments after each data byte is transferred. the master generates a stop condition to terminate the data write. 2) slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the IDT1337G while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer (see the ?data read?slave transmitter mode? figure). the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7-bit IDT1337G address, which is 1101000, followed by the direction bit (r/w ), which is 1 for a read. after receiving and decoding the slave address byte the slave outputs an acknowledge on the sda line. the IDT1337G then begins to transmit data starting with the register address pointed to
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 12 IDT1337G rev m 073013 by the register pointer. if the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. the IDT1337G must receive a ?not acknowledge? to end a read. data write ? slave receiver mode data read (from current pointer location) ? sla ve transmitter mode data read (write pointer, then read) ? slave receive and transmit
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 13 IDT1337G rev m 073013 handling, pcb layout, and assembly the IDT1337G package contains a quartz tuning-fork crystal. pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avioded. ultrasonic cleaning equipment should be avioded to prevent damage to the crystal. avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. all nc (no connect) pins must be connected to ground. moisture-sensitive packages are shipped from the factory dry-packed. handling instructions listed on the package label must be followed to prevent damage during reflow. refer to the ip c/jedec j-std-020 standard for moisture-sensitive device (msd) classifications. absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the IDT1337G. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended dc op erating conditions item rating voltage range (on any pin relative to ground) -0.3 v to +6.0 v storage temperature -55 to +125 ? c soldering temperature 260 ? c ambient operating temperature (industrial) -40 to +85c parameter symbol conditions min. typ. max. units vcc supply voltage v cc full operation 1.8 3.3 5.5 v v cct timekeeping 1.3 1.8 v ambient operating temperature (industrial) t a -40 +85 ? c logic 1 v ih scl, sda 0.8vcc vcc + 0.3 v inta , sqw/intb 5.5 logic 0 v il -0.3 +0.3vcc v
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 14 IDT1337G rev m 073013 dc electrical characteristics unless stated otherwise, vcc = 1.8 v to 5.5 v , ambient temp. -40 to +85 ? c, note 1 dc electrical characteristics unless stated otherwise, vcc = 1.3 v to 1.8 v , ambient temp. -40 to +85 ? c (industrial), note 1 parameter symbol conditions min. typ. max. units input leakage i li note 2 -1 +1 a i/o leakage i lo note 3 -1 +1 a logic 0 output vol = 0.4 v i ol note 3 3 ma active supply current i cca note 4 5 150 a standby current i ccs notes 5, 6 1.5 a parameter symbol conditions min. typ. max. units timekeeper curr ent (oscillator enabled) i cctosc notes 5, 7, 8, 9 725 900 na data-retention current (oscillator disabled) i cctddr notes 5, 9 300 na
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 15 IDT1337G rev m 073013 ac electrical characteristics unless stated otherwise, vcc = 1.8 v to 5.5 v , ambient temp. -40 to +85 ? c, note 1 parameter symbol conditions min. typ. max. units scl clock frequency f scl fast mode 100 400 khz standard mode 0 100 bus free time between a stop and start condition t buf fast mode 1.3 s standard mode 4.7 hold time (repeated) start condition, note 10 t hd:sta fast mode 0.6 s standard mode 4.0 low period of scl clock t low fast mode 1.3 s standard mode 4.7 high period of scl clock t high fast mode 0.6 s standard mode 4.0 setup time for a repeated start condition t su:sta fast mode 0.6 s standard mode 4.7 data hold time, notes 11, 12 t hd:dat fast mode 0 0.9 s standard mode 0 data setup time, note 13 t su:dat fast mode 100 ns standard mode 250 rise time of both sda and scl signals, note 14 t r fast mode 20 + 0.1c b 300 ns standard mode 1000 fall time of both sda and scl signals, note 14 t f fast mode 20 + 0.1c b 300 ns standard mode 300 setup time for stop condition t su:sto fast mode 0.6 s standard mode 4.0 capacitive load for each bus line, note 14 c b 400 pf i/o capacitance (sda, scl) c i/o note 15 10 pf 32.768 khz clock accuracy with external crystal t a =25c v cc =3.3 v 10 ppm 32.768 khz clock accuracy with internal crystal t a =25c v cc =3.3 v (crystal accuracy 20ppm) 30 ppm
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 16 IDT1337G rev m 073013 note 1 : limits at -40c are guaranteed by design and are not production tested. note 2 : scl only. note 3 : sda, inta , and sqw/intb . note 4 : i cca ?scl clocking at maximum frequency = 400 khz, vil = 0.0v, vih = vcc. note 5 : specified with the i 2 c bus inactive, vil = 0.0v, vih = vcc. note 6 : sqw enabled. note 7 : specified with the sqw function disabled by setting intcn = 1. note 8 : using recommended crystal on x1 and x2. note 9 : the device is fully accessible when 1.8 < vcc < 5.5 v. time and date are maintained when 1.3 v < vcc < 1.8 v. note 10 : after this period, the first clock pulse is generated. note 11 : a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefi ned region of the falling edge of scl. note 12 : the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 13 : a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > to 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su:dat = 1000 + 250 = 1250 ns before the scl line is released. note 14 : c b ?total capacitance of one bus line in pf. note 15 : guaranteed by design. not production tested.
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 17 IDT1337G rev m 073013 timing diagram
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 18 IDT1337G rev m 073013 typical operating characteristics thermal characteristics for 8soic thermal characteristics for 8msop parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 150 ? c/w ? ja 1 m/s air flow 140 ? c/w ? ja 3 m/s air flow 120 ? c/w thermal resistance junction to case ? jc 40 ? c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 95 ? c/w thermal resistance junction to case ? jc 48 ? c/w icc vs vcc 200 300 400 500 600 700 800 900 1.3 2.3 3.3 4.3 5.3 vcc (v) icc (na) intcn=1 intcn=0 icca vs vcc 0 2 4 6 8 10 1.3 2.3 3.3 4.3 5.3 vcc (v) icc (ua) icca icc vs temperature 200 300 400 500 600 700 800 -40-20 0 20406080 temperature (c) icc (na) intcn=1 intcn=0 oscillator frequency vs vcc (as measured on one idt1337c sample) 32768.3 32768.32 32768.34 32768.36 32768.38 32768.4 1.3 2.3 3.3 4.3 5.3 vcc(v) frequency (hz) freq
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 19 IDT1337G rev m 073013 thermal characteristics for 16soic thermal characteristics for 16-pin vfqfpn parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 120 ? c/w ? ja 1 m/s air flow 115 ? c/w ? ja 3 m/s air flow 105 ? c/w thermal resistance junction to case ? jc 58 ? c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ? ja still air 69.4 ? c/w ? ja 1 m/s air flow 60.7 ? c/w ? ja 2.5 m/s air flow 54.4 ? c/w thermal resistance junction to case ? jc 9.7 ? c/w
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 20 IDT1337G rev m 073013 marking diagram (8 msop) marking diagram (16 soic) marking diagram (8 soic) marking diagram (16 vfqfpn) notes: 1. # = product stepping. 2. $ = mark code. 3. ** = sequential lot code. 4. yyww is the last two digits of the year and week that the part was assembled. 5. ?xxx? = traceability (lot code). 6. ?g? denotes rohs compliant package. 7. ?i? denotes industrial grade. 8. bottom marking: country of origin if not usa. 7ggi yyww$ 1 8 9 16 idt 1337gc srgi yyww**$ idt 1337g dcgi yyww$ 14 5 8 xxx yww$ 37gi
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 21 IDT1337G rev m 073013 package outline and package dimensions (8-pin soic, 150 mil. body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c ? c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 ? 0 ? 8 ? 0 ? 8 ?
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 22 IDT1337G rev m 073013 package outline and package dimensions (8-pin msop, 3.00 mm body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e1 e seating plane a 1 a a 2 e - c - b aaa c ? c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a--1.10--0.043 a1 0 0.15 0 0.006 a2 0.79 0.97 0.031 0.038 b 0.22 0.38 0.008 0.015 c 0.08 0.23 0.003 0.009 d 3.00 basic 0.118 basic e 4.90 basic 0.193 basic e1 3.00 basic 0.118 basic e 0.65 basic 0.0256 basic l 0.40 0.80 0.016 0.032 ? 0 ? 8 ? 0 ? 8 ? aaa - 0.10 - 0.004
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 23 IDT1337G rev m 073013 package outline and package dimensions (16-pin soic, 300 mil body) package dimensions are kept current with jedec publication no. 95 index area 1 2 16 d e1 e seating plane a 1 a a 2 e - c - b aaa c ? c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a -- 2.65 -- 0.104 a1 0.10 -- 0.0040 -- a2 2.05 2.55 0.081 0.100 b 0.33 0.51 0.013 0.020 c 0.18 0.32 0.007 0.013 d 10.10 10.50 0.397 0.413 e 10.00 10.65 0.394 0.419 e1 7.40 7.60 0.291 0.299 e 1.27 basic 0.050 basic l 0.40 1.27 0.016 0.050 ? 0 ? 8 ? 0 ? 8 ? aaa - 0.10 - 0.004
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 24 IDT1337G rev m 073013 package outline and package dimensions (16-pin vfqfpn 3x3mm) package dimensions are kept current with jedec publication no. 95 millimeters symbol min max a0.801.00 a1 0 0.05 a3 0.20 reference b0.180.30 e 0.50 basic n16 n d 4 n e 4 d x e basic 3.00 x 3.00 d2 1.55 1.80 e2 1.55 1.80 l0.300.50 sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 25 IDT1337G rev m 073013 ordering information the 1337gc packages are rohs compliant. packages without th e integrated crystal are pb-free; packages that include the integrated crystal (as designated with a ?c ? before the two-letter package code) may in clude lead that is exempt under rohs requirements. the lead fini sh is jesd91 category e3. ?g? is the device revision d esignator and will not correlat e to the datasheet revision. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number markings shipping packaging package temperature 1337gdvgi see page 20 tubes 8-pin msop -40 to +85 ? c 1337gdvgi8 tape and reel 8-pin msop -40 to +85 ? c 1337gcsrgi tubes 16-pin soic -40 to +85 ? c 1337gcsrgi8 tape and reel 16-pin soic -40 to +85 ? c 1337gdcgi tubes 8-pin soic -40 to +85 ? c 1337gdcgi8 tape and reel 8-pin soic -40 to +85 ? c 1337gnlgi tubes 16-pin vfqfpn -40 to +85 ? c 1337gnlgi8 tape and reel 16-pin vfqfpn -40 to +85 ? c
IDT1337G real-time clock with i 2 c serial interface rtc idt? real-time clock with i 2 c serial interface 26 IDT1337G rev m 073013 revision history rev. date originator description of change a 12/12/08 j.sarma new device. preliminary release. b 01/28/09 a. tsui added 16-pin qfn package and ordering info. c 02/04/09 a. tsui updated 16-pin qfn pinout. d 04/03/09 a. tsui added 5a typ. to active supply current spec. e 05/26/09 a. tsui added top-side markings. f 11/10/09 added ?handling, pcb layout, and assembly? section. g 11/16/09 a. tsui changed series resistance parameter from 50 to 80 kohm. h 08/02/10 a. tsui added extended temperature range for 8-pin soic. j 03/01/11 a. tsui updated standard mode specs for ?r ise/fall time of both sda and scl signals?. k 09/20/12 j. chao 1. moved from fab4 to tsmc. qa requested change in the marking of only the 16-pin soic device with internal crystal to add ?a? due to the fact that tsmc uses a different crystal than fab4. notification of a change in orderables was initiated with pcn a1208-06. 2. . updated 16-pin soic marking diagra m and ordering information to include "a". l 10/24/12 a. tsui 1. updated idd specs per tsmc?s characterization data. 2. updated top-side device markings. l 06/26/13 j. chao 1. added verbiage for bit0, bit1, and bit2 descriptors for further clarification. 2. added "alarm/interrupt table for the aforementioned bits for further clarification. 3. no change to revision letter - only the revision date. m 07/30/13 j. chao removed all references to extended temperature range (-40 to 105c); no longer supporting extended temperature.
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